1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device equipped with a redundant selection line that replaces a selection line such as a defective word line.
2. Description of Related Art
In DRAM (Dynamic Random Access Memory), which is a typical semiconductor memory device, a very large number of memory cells are contained. In recent years, there have been products with a storage capacity of 1 G bits or more per chip. Therefore, it is difficult to make all the memory cells operate properly, and some of the memory cells become defective in production process. Defective memory cells are replaced with spare memory cells in production process. As a result, the semiconductor memory device is shipped as a normal product.
In general, the replacement of memory cells is performed in units of word or bit lines. That is, a defective word line is replaced with a redundant word line, and a defective bit line with a redundant bit line. To each of the redundant word lines and redundant bit lines, a corresponding hit signal generation circuit is assigned. The hit signal generation circuit which may be also referred to as an address determination circuit. If an address for which an access request has been made matches an address of a defective word line or defective bit line, a hit signal output from a corresponding hit signal generation circuit becomes activated. As a result, the redundant word line or redundant bit line is selected.
The hit signal generation circuit usually includes a fuse circuit, which stores addresses of defective word lines or defective bit lines, as well as an enable fuse circuit, which selects whether or not to use the hit signal generation circuit. For example, if the enable fuse circuit is in a state of being programmed, then the hit signal generation circuit is in a state of being used. As a result, a comparison of an address to which access is requested with an address of a defective word line or defective bit line is effectively made. By contrast, if the enable fuse circuit is in a state of not being programmed, then the hit signal generation circuit is in a state of not being used. As a result, a comparison of an address to which access is requested with an address of a defective word line or defective bit line is not made. The use of such an enable fuse circuit prevents an incorrect replacement operation.
However, if each hit signal generation circuit is provided with an enable fuse circuit, a required area occupied by the hit signal generation circuits on the semiconductor chip increases accordingly. To solve the problem, what is proposed in Japanese Patent Application Laid-Open No. 2006-179114 is a hit signal generation circuit from which an enable fuse circuit has been removed. In the hit signal generation circuit disclosed in Japanese Patent Application Laid-Open No. 2006-179114, if any one of a plurality of fuse circuits that store addresses of defective word lines or defective bit lines is in the state of being programmed, then the hit signal generation circuit is regarded as being in the state of being used, thereby requiring no enable fuse circuit.
However, in the hit signal generation circuit disclosed in Japanese Patent Application Laid-Open No. 2006-179114, in order to make a determination as to whether or not the hit signal generation circuit is in the state of being used, a logical sum and synthesis operation of all outputs of a fuse circuit used for storing addresses is required. Therefore, a relatively large number of circuit elements are required. Therefore, while the enable fuse circuit is eliminated, a semiconductor device that can make a determination as to whether or not the hit signal generation circuit is in the state of being used with the use of a smaller number of circuit elements is desirable.